査読付き国際会議のプロシーディング、Extended Abstract
- 1) G. Tanaka, R. Nakane, T. Yamane, S. Takeda, D. Nakano, S. Nakagawa, A. Hirose, “Nonlinear Dynamics of Memristive Networks and its Application to Reservoir Computing”, Proc. Int. Symp. Nonlinear Theory and its Applications (NOLTA, Cancun, Dec. 4-7, Oral, Dec. 5), pp. 182-185 (2017).
- 2) A. Hirose, S. Takeda, T. Yamane, D. Nakano, S. Nakagawa, R. Nakane, and G. Tanaka, “Complex-Valued Neural Networks to Realize Energy-Efficient Neural Networks Including Reservoir Computing”, Proc. Int. Symp. Nonlinear Theory and its Applications (NOLTA, Cancun, Dec. 4-7, Oral, Dec. 5), pp. 186-188 (2017).
- 3) G. Tanaka, R. Nakane, T. Yamane, S. Takeda, D. Nakano, S. Nakagawa, and A. Hirose, “Waveform Classification by Memristive Reservoir Computing”, Proc. Int. Conf. Neural Information Processing (ICONIP, Guangzhou, Nov. 14-18, Oral, Nov. 15), pp. 457-465 (2017).
- 4) A. Hirose, S. Takeda, T. Yamane, D. Nakano, S. Nakagawa, R. Nakane, and G. Tanaka, “Complex-valued neural networks for wave-based realization of reservoir computing”, Proc. Int. Conf. Neural Information Processing (ICONIP, Guangzhou, Nov. 14-18, Oral, Nov. 15), pp. 449-456 (2017).
- 5) T. Yamane, S. Takeda, D. Nakano, G. Tanaka, R. Nakane, A. Hirose, and S. Nakagawa, “Simulation Study of Physical Reservoir Computing by Nonlinear Deterministic Time Series Analysis”, Proc. Int. Conf. Neural Information Processing (ICONIP, Guangzhou, Nov. 14-18, Oral, Nov. 15), pp. 639-647 (2017).
- 6) G. Tanaka, R. Nakane, T. Yamane, D. Nakano, S. Takeda, S. Nakagawa and A. Hirose, "Exploiting Heterogeneous Units for Reservoir Computing with Simple Architecture", International Conference on Neural Information Processing(ICONIP 2016, Proceedings),(2016), pp. 187 -194.
- 7) T. Yamane, S. Takeda, D. Nakano, G. Tanaka, R. Nakane, S. Nakagawa and A. Hirose, "Dynamics of Reservoir Computing at the Edge of Stability", International Conference on Neural Information Processing(ICONIP 2016, Proceedings),(2016), pp. 205-212.
- 8) S. Takeda, D. Nakano, T. Yamane, G. Tanaka, R. Nakane, A. Hirose and S. Nakagawa, "Photonic Reservoir Computing Based on Laser Dynamics with External Feedback", International Conference on Neural Information Processing(ICONIP 2016, Proceedings),(2016), pp. 222-230.
- 9) R. Mori, G. Tanaka, R. Nakane, A. Hirose and K. Aihara, "Computational Performance of Echo State Networks with Dynamic Synapses", International Conference on Neural Information Processing(ICONIP 2016, Proceedings),(2016), pp. 264-271.
- 10) G. Tanaka, T. Yamane, D. Nakano, R. Nakane, and Y. Katayama, “Hopfield-Type Associative Memory with Sparse Modular Networks”, L.C. Kiong et al. (Eds.) Proc. 2014 Int. Conf. Neural Information Processing (ICONIP), Part I, Lecture Notes in Computer Science, vol. 8834, pp. 255-262 (2014).
- 11) Minsoo Kim, Yuki Wakabayashi, Ryosho Nakane, Masafumi Yokoyama, Mitsuru Takenaka, and Shinichi Takagi. “High Ion/Ioff Ge-source ultrathin body strained-SOI Tunnel FETs-impact of channel strain, MOS interfaces and back gate on the electrical properties”. Tech. Dig. International Electron Device Meeting (IEDM) pp. 13.2.1-4.
- 12) S. Kim, Y. Ikku, M. Yokoyama, R. Nakane, J. Li, Y.-C. Kao, M. Takenaka and S. Takagi, High Performance InGaAs-On-Insulator MOSFETs on Si by Novel Direct Wafer Bonding Technology Applicable to Large Wafer Size Si,2012 Symposia on VLSI Technology and Circuit, the Hilton Hawaiian Village, Honolulu, June 9-12, 2014, 4.4, Technical Digest 2pages.
- 13) R. Nakane, Y. Shuto, H. Sukegawa, Z.C. Wen, S. Yamamoto, S. Mitani, M. Tanaka, K. Inomata, and S. Sugahara, “Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service - A new route to more-than-Moore research ?”, IEEE 43rd European Solid-State Device Research Conference (ESSDERC) 2013, Bucharest, Romania, September 16-20, 2013, Paper 1272, Conference Digest 2pages.
- 14) S. H. Kim, M. Yokoyama, R. Nakane, O. Ichikawa, T. Osada, M. Hata, M. Takenaka and S. Takagi, “High Performance Extremely-thin Body InAs-On-Insulator MOSFETs on Si with Ni-InGaAs Metal S/D by Contact Resistance Reduction Technology”, Kyoto, Japan, 11-13 June, 2013, Presentation 5-2, Technical Digest T52-53.
- 15) M. S. Kim, Y. H. Kim, M. Yokoyama, R. Nakane, S. H. Kim, M. Takenaka, S. Takagi, “Tunnel Field-Effect Transistors with Germanium/Strained-Silicon Hetero-Junctions for Low Power Applications”, The 8th International Conference on Silicon Epitaxy and Heterostructures (ICSI-8), Fukuoka, Japan, June 2-7, 2013, Presentation P1-26, Proceeding pp. 197-198.
- 16) Y. Shuto, S. Yamamoto, H. Sukegawa, Z.C. Wen, R. Nakane, S. Mitani, M. Tanaka, K. Inomata, and S. Sugahara, “Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices”, IEEE International Electron Devices Meeting (IEDM) 2012, San Francisco, CA, USA, December 10-12, 2012, Conference Digest pp. 685-688.
- 17) S. H. Kim, M. Yokoyama, N. Taoka, R. Nakane, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka and S. Takagi, “Sub-60 nm deeply scaled Extremely-thin Body InxGa1-xAs-On-Insulator MOSFETs on a Si substrate with Ni-InGaAs metal S/D and MOS Interface Buffer Engineering”, 2012 Symposia on VLSI Technology and Circuit VLSI, Honolulu, June 12-14, 2012, 21.1, Technical Digest pp. 177-178.
- 18) S. H. Kim, M.Yokoyama, N.Taoka, R.Nakane, T. Yasuda, M. Ichikawa, N. Fukuhara, M. Hata, M.Takenaka and S.Takagi, “Enhancement Technologies and Physical Understanding of Electron Mobility in III-V n-MOSFETs with Strain and MOS Interface Buffer Engineering”, IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, December 5-7, 2011, Conference Digest pp. 311-314.
- 19) S. H. Kim, M. Yokoyama, N. Taoka, R. Iida, S. Lee, R. Nakane, Y. Urabe, N. Miyata, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M. Takenaka and S. Takagi, “Self-aligned metal S/D InP MOSFETs using metallic Ni-InP alloy”, 23rd International Conference on Indium Phosphide and Related Materials (IPRM), Berlin, Germany, May 22-26, 2011, Presentation No. 42, Proceedings 4pages.
- 20) S. H. Kim, M. Yokoyama, N. Taoka, R. Iida, S. Lee, R. Nakane, Y. Urabe, N. Miyata, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M. Takenaka and S. Takagi, “High performance Extremely-thin Body III-V-On-Insulator MOSFETs on a Si substrate with Ni-InGaAs metal S/D and MOS Interface Buffer Engineering”, 2011 Symposia on VLSI Technology and Circuit, Kyoto, Japan, June 13-17, 2011, 4A-2, Technical Digest pp. 58-59.
- 21) J.-K. Suh, R. Nakane, N. Taoka, M. Takenaka and S. Takagi, “Highly-Strained SGOI p-Channel MOSFETs Fabricated by Applying Ge Condensation Technique to Strained-SOI Substrates”, 37th Device Research Conference (DRC), Santa Barbara, CA, USA, June 20-22, 2011, Conference Digest pp. 235-236.
- 22) S. H. Kim, M.Yokoyama, N.Taoka, R. Iida, S. Lee, R.Nakane, Y. Urabe, N. Miyata, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M.Takenaka and S.Takagi, “Self-aligned metal Source/Drain InxGa1-xAs n-MOSFETs using Ni-InGaAs alloy”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA USA, Dec. 6-8, 2010, Conference Digest pp. 596-599.
- 23) K. Morii, T. Iwasaki, R. Nakane, M. Takenaka and S. Takagi, “High Performance GeO2/Ge nMOSFETs with Source/Drain Junctions Formed by Gas Phase Doping”, IEEE International Electron Devices Meeting (IEDM)2009, Hilton Baltimore, Baltimore, MD, December 7-9, 2009, Conference Digest pp. 681-684.
- 24) S. H. Kim, S. Nakagawa, T. Haimoto, R. Nakane, M. Takenaka and S. Takagi, “Metal Source/Drain Inversion-mode InP MOSFETs”, 67th Device Research Conference (DRC), The Pennsylvania State University, Pennsylvania, USA, June 22 ? 24, 2009, Conference Digest pp. 115-116.
- 25) R. Nakane, T. Harada, K. Sugiura, S. Sugahara and M. Tanaka, “Magneto resistance in MOSFETs with ferromagnetic MnAs source and drain contacts: Spin injection and transport in Si MOS channels”, The 66th Device Research Conference (66th DRC), Santa Barbara, CA, USA, June 23-25, 2008, V.A-7, Conference Digest pp. 227-228.
- 26) Y. Nakakita, R. Nakane, T. Sasada, H. Mastubara, M. Takenaka, and S. Takagi, “Interface-Controlled Self-Align Source/Drain Ge pMOSFETs Using Thermally-Oxidized GeO2 Interfacial Layers”, IEEE International Electron Devices Meeting (IEDM) 2008, San Francisco, CA, USA, Dec. 15-17, 2008, Conference Digest pp. 877-880.