Masaaki Tanaka Laboratory, Dept of Electronic Engineering, The University of Tokyo - Activities

Masaaki Tanaka Laboratory, Dept of Electronic Engineering, The University of Tokyo

Research Activities(revised December 2006)

Research Field

Our main research field is "Spin-Electronics" or "Spintronics", in which we try to utilize the spin degrees of freedom in artificially synthesized materials. We are studying epitaxial growth, structural characterizations, electronic/optical/magnetic/spin-related properties (in particular, spin-dependent transport and mageto-optical properties), and device applications of various new structures. The following are some of the structures and devices we are working on:


Research Subjects

Ferromagnetic Metal / Semiconductor Heterostructures and Spin Transistors
M. Tanaka, S. Sugahara, R. Nakane, K. Sugiura, J. Kondo, and P-N. Hi

It is expected that the feasibility of growing monocrystalline high-quality ferromagnetic thin films on semiconductors leads to a new class of materials which combines the properties both of semiconductors and of ferromagnets, giving rise to new applications. We have successfully grown ferromagnetic MnAs films with hexagonal NiAs-type crystal structure on Si and GaAs substrates by MBE. Furthermore, we have successfully grown MnAs/III-V(GaAs,AlAs)/MnAs trilayer structures having good crystalline quality on Si(111) and GaAs (111) substrates, and have observed the spin-valve effect and tunneling magnetoresistance (TMR), which can lead to the application to magnetic-field sensors and magnetic random access memory (MRAM). Furthermore, we proposed and analyzed a new class of silicon-MOS based spin transistors (Spin MOSFET) and their application to ultrahigh density nonvolatile memory and reconfigurable logic devices. We are investigating device processes for realizing Si-based spin devices.

III-V Based Ferromagnetic Semiconductors (GaMn)As, (InGaMn)As, Mn-delta-doped GaAs, and their Ultrathin Quantum Heterostructures
A.M. Nazmul, S. Sugahara, S. Ohya, H-T. Lin, Y. Shuto, and M. Tanaka

We have successfully grown a new III-V based magnetic semiconductor (GaMn)As by low-temperature molecular beam epitaxy (LT-MBE), in which strong non-equilibrium growth conditions allow a large amount of Mn atoms to be incorporated into the host lattice of GaAs. Ternary alloys of (Ga1-xMnx)As were obtained when the Mn content x was less than 0.08, and all of them showed p-type conduction. By magnetization and magneto-transport studies on the GaMnAs, ferromagnetic order was found at low temperature and the Curie temperature TC was 10 - 100 K. This is a new class of materials having properties both of III-V semiconductors and of ferromagnetic materials, providing new opportunities to study the interaction between carriers and local spins. Furthermore, we have grown magnetic(GaMnAs) / nonmagnetic(AlAs) semiconductor superlattices (SLs), and the SLs are shown to have quantum well states. More recently, we have successfully grown a new quaternary alloy magnetic semiconductor (InGaMn)As, and have found that it is ferromagnetic with TC ~ 80K. In (InGaMn)As, the lattice constant and the bandgap can be changed, and it can be grown on lattice-matched InP substrates, thus having good compatibility with optical communication devices. More recently, we have realized high TC of 172-250 K in Mn-delta-doped GaAs / p-AlGaAs heterostructures, which are the highest values ever reported in III-V based materials. Recently, we find out the giant planar Hall effect in Mn-delta-doped GaAs / p-AlGaAs heterostructures and clarified the magnetic anisotropy. Such new magnetic quantum heterostructures are very attractive in view of fundamental research as well as potential applications to "spintronics".

Magnetic Tunnel Junctions using Ferromagnetic Semiconductor Heterostructures and Large Tunneling Magneto-Resistance
S. Ohya, P-N. Hi, Y. MIZUNO, and M. Tanaka

We have observed very large tunneling magnetoresistance (TMR) in epitaxially grown GaMnAs/AlAs/GaMnAs ferromagnetic semiconductor tunnel junctions. Large TMR ratios more than 70% were obtained in junctions with a very thin (<1.6 nm) AlAs tunnel barrier when the magnetic field was applied along the [100] axis in the film plane. The TMR was found to rapidly decrease with increasing the barrier thickness, which is explained by calculations assuming that the parallel wave vector k// of carriers is conserved in tunneling. Recently, we observed negative TMR and oscillations of the TMR ratio (with varying the AlAs thickness) in GaMnAs/AlAs/InGaAs/AlAs/GaMnAs double-barrier ferromagnetic tunnel junctions, for the first time in magnetic semiconductor systems. This is caused by the appearance of resonant tunneling and TMR effects at the same time. Realization of such large spin-dependent tunneling in semiconductor heterostructures, that is spin injection from one semiconductor layer to another semiconductor layer via tunneling, is an very significant step towards future spintronics, in which one tries to use the spin degree of freedom in semiconductor devices.

Semiconductor-Based Magneto-Photonic Crystals: Ferromagnet(MnAs)/III-V Semiconductor Hybrid Multilayer Structures: Fabrication, Magneto-optical , Magnet-resistive Properties, and Device Applications
M. Yokoyama, P-N. Hi, S. Ohya T. Ogawa, T. Amemiya, H. Shimizu, and M. Tanaka

We have fabricated ferromagnet(MnAs)/III-V semiconductor(GaAs) granular structures, hereafter GaAs:MnAs, by annealing (GaMn)As at 500 - 800oC. During the annealing process, MnAs ferromagnetic clusters with diameters of a few nm were formed in a matrix of GaAs (or GaMnAs), exhibiting a superparamagnetic behavior. We have established the fabrication process and have measured magneto-optic properties. Furthermore, we have fabricated GaAs:MnAs sandwiched by GaAs/AlAs distributed Bragg Reflectors (DBRs), and have showed significant enhancement of magneto-optical effect by using multiple interference and localization of light in the GaAs:MnAs magnetic layer. This structure offers new opportunity for the application to spin-controlled photonic devices based on III-V compound semiconductors. Recently, we have found extremely large positive magnetoresistance of 600 % at room temperature in the GaAs:MnAs granular structures, and further investigations are underway.

Group-IV-based Spintronics Materials and Device Processes
R. Nakane, K. Sugiura, Y. Shuto, S. Yada, S. Sugahara, and M. Tanaka

It is no doubt that Si and group-IV semiconductors will be continuously important in the future, because they are used for MOS transistors and integrated circuits. We study the fabrication of group-IV (Si and Ge) based magnetic semiconductors and ferromagnets with high spin polarization, such as half metals, which are compatible with group-IV semiconductors, and their applications to spin-device processes. We have grown GeMn and clarified the origin of its ferromagnetism, successfully fabricated ferromagnetic amorphous semiconductor GeMn. Also, we have successfully grown a new ferromagnetic semiconductor GeFe and clarified its microscopic structure and magneto-optical properties. Recently, we have successfully fabricated ferromagnetic Fe3Si on silicon-on-insulator (SOI) substrates, and developed spin MOS devices.

New spin transistors (eg. spin-MOSFET) and reconfigurable logic devices
S. Sugahara, R. Nakane, K. Sugiura, T. Harada, T. Matsuno, and M. Tanaka

We have recently proposed new class of spin transistors, referred to as spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs), and thier integrated circuit applications. The fundamental device structures and theoretically predicted device performance are theoretically calculated predicted. The spin MOSFETs potentially exhibit significant magnetotransport effect such as large magneto-current and also satisfy important requirements for integrated circuit applications such as high transconductance, low power-delay product, and low off-current. Since the spin MOSFETs can perform signal processing and logic operations and can store digital data using both of the charge transport and the spin degree of freedom, they are expected to be building blocks for a memory cell and logic gates on spin-electronic integrated circuits. Novel spin-electronic integrated circuit architectures for nonvolatile memory and reconfigurable logic employing spin MOSFETs are also proposed. A reconfigurable NAND/NOR logic gate can be realized by using a spin MOSFET as a driver or an active load of a complimentary MOS (CMOS) inverter with a neuron MOS input stage. Its logic function can be switched by changing the relative magnetization configuration of the ferromagnetic source and drain of the spin MOSFET. A reconfigurable logic gate for all symmetric Boolean functions can be configured using only five CMOS inverters including four spin MOSFETs. The operation of these reconfigurable logic gates was confirmed by numerical simulations using a simple device model for the spin MOSFETs.


Prof. Masaaki Tanaka
Department Electronic Engineering, The University of Tokyo
7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

Phone: +81-3-5841-6728 or +81-3-5841-6729 (lab)
Fax+81-3-5803-3975, : +81-3-5841-6724
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Curriculum Vitae

1984 March, BS, Electronic Engineering, The University of Tokyo
1986 March, MS, Electronic Engineering, The University of Tokyo
1989 March, Ph.D, Electronic Engineering, The University of Tokyo
The thesis title “Atomically Controlled Growth of Semiconductor Heterostructures by Molecular Beam Epitaxy and Their Electronic Properties” (Dissertation Supervisor: Prof. Hiroyuki Sakaki).
1990 April, Lecturer, Dept Electrical Engineering, The University of Tokyo
1992 March - 1994 March, Visiting Research Scientist at Bell Communications Research (Bellcore), New Jersey, USA.
1994 April – 2004 September, Associate Professor, Dept Electronic Engineering, Graduate School of Engineering, The University of Tokyo
1995 October - 1998 September, Researcher at the PRESTO Program on “Fields and Reactions” funded by Japan Science & Technology Corporation.
2001 December - 2004 November, Researcher at the PRESTO Program on “Light and Control” funded by Japan Science & Technology Corporation.
2004 October - present, Professor, Dept Electronic Engineering, Graduate School of Engineering, The University of Tokyo

Lecture Courses by M. Tanaka at the University of Tokyo

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